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Sr. Design Verification Engineer

Location
Sunnyvale, CA
Experience
2-4
Years
Job Code
CA-2020-1

Preferred Education:

Bachelor’s degree in Computer Science, Engineering, Computer Information Systems, Computer Engineering, Software Engineering or a closely related field of Engineering

Area of Expertise:

SSD, PCIe, Ethernet, HBM-DDR, Processor verification, floating-point computational unit, C/C++, and Scripting (Perl, Python).

 

Roles & Responsibilities:

  • Develop a block-level test plan, UVM test bench components such as agents (drivers/monitors), scoreboard, constrained random test cases based on UVM sequences, assertions.
  • Develop and close functional coverage, code coverage.
  • Independently execute on test plan, run simulations, and debug/triage regression failures.
  • Develop required scripting in Perl or python.
  • Creation of verification environments using UVM methodology.
  • Pre-silicon functional verification at the block, chip, and system level.
  • Creation of test plan.
  • Functional coverage and code coverage closure.
  • Writing scripts to check regression results.
  • Performance measurement of blocks.
  • Gate level simulation.
  • Advanced Test development using SSD, PCIe, Ethernet, HBM-DDR, Processor verification, floating point computational unit, C/C++, and Scripting (Perl, Python).

 

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