Preferred Education:

• Requires a Bachelor’s degree in Electrical Engineering, Electronics and Communication Engineering, Computer Science, or a related field.

Location:

• CalSoft Labs, Inc., 2890, Zanker Road, Suite 200, San Jose, CA 95134, USA.

Contact Person:

• jobsus@altencalsoftlabs.com

Experience:

• BS 3 to 5 years

Roles & Responsibilities:

• Develop test plan for functional , develop the scalable testbench using the HVLs, test case development, debugging, coverage model development, coverage closure.
• Perform comprehensive pre-silicon test planning, testbench development using the advanced verification methodology such as SystemVerilog-OVM, SystemVerilog-UVM, assertion development.
• Perform digital design and block level verification flow developments as well as chip level verification.
• Work on Multiple ASIC Verification Languages like System Verilog, Verilog, perl scripting to write automate scripts
• Work on debugging of amba protocols (APB, AHB, AXI)
• Work with the digital design team, to complete the verification successfully.
• Act as part of multiple tape-outs with high quality verification
• Demonstrate strong in logic coding and testbench/testcase issues debugging
• Write assertion checkers and formal connectivity checks
• Utilize RAL model for design register access; and
• Utilize EDA tools like Synopsis Verdi, VCS, Cadance.