Integrated Hardware and Software Tools Vital for Debugging RISC-V Processors

Published Date

November 8, 2023


5 minutes

Written By

ACL Digital

Debugging a RISC-V processor composed of dozens or even hundreds of cores, executing billions of instructions per second, presents significant challenges. Is the software functioning as intended? Is memory being utilized proficiently? What factors are contributing to hardware and software deadlocks within the system? Are there opportunities for optimizing instructions? How can sporadic, elusive issues be traced and resolved? Do the verification team’s observations align with those of the firmware engineers and application developers?

Although software tools offer solutions, they frequently utilize system resources, potentially impacting application performance, leading to erratic software behavior, or necessitating extensive instrumentation to gather the necessary information for identifying the root cause of an issue.

SoC development teams are progressively advocating for the mandatory inclusion of a processor hardware trace solution within every RISC-V core. This feature enables the reconstruction of instruction execution sequences. However, the substantial volume of generated trace data can swiftly overpower the system, resulting in the loss of trace information or requiring additional on-chip storage and system resources.

Software and Hardware

Traditional software tools and methodologies continue to serve as the foundation for debugging, yet their seamless integration with hardware is imperative when addressing issues within intricate processors. The combined utilization of hardware and software tools can offer a conclusive solution, ensuring the acquisition of precise and resilient data over extended periods, spanning weeks or even months. This approach safeguards against introducing further errors during verification, application development, and testing. The amassed data can be transmitted to the host via high-bandwidth output interfaces (such as USB3, SerDes and PCIe) to reconstruct the device’s state at the occurrence of specific events.

Embedded and host software can employ low-bandwidth input interfaces, such as USB2 and JTAG, to intake system data, comprising executable files, code uploads, or hardware configuration specifics. The integration of hardware and software tools facilitates real-time examination of crucial issues, whether on or off the chip, leveraging the data captured by the hardware. Furthermore, this data can be stored off-chip to enable in-depth analysis, performance optimization, and review of code coverage.

Resourceful Hardware Trace

Irrespective of the chosen output interfaces, handling the substantial volume of trace data is pivotal. Rather than attempting to transfer every byte of data to a host system, the hardware trace tools should be able to filter the captured trace, extracting only the pertinent transactions. Subsequently, employing highly optimized compression techniques becomes crucial to curtail the volume of transferred data – in this context, every byte is significant.

As the data is commonly captured in bursts, the hardware requires features that mitigate potential device bottlenecks and ensure data integrity while transferring to software tools. The hardware must be capable of capturing trace data from multiple sources concurrently while providing essential timestamps and metadata. It ensures the software can accurately reconstruct the device’s behavior at specific events.

Delivering Supplementary Features

Processor debugging extends beyond processor tracing. Hardware can encompass additional modules that intercommunicate in real time, collectively identifying significant events. For instance, a processor module overseeing function calls from the host software (e.g., stop, start, and breakpoints) can activate the trace encoder or direct a DMA module to retrieve system memory values when an event occurs. This hardware DMA module can also speed up uploading executable ELF files, running new software iterations, or enabling the reset register.

Hardware counters offer a highly effective method to capture valuable data, such as the frequency of instruction execution or function calls. By integrating hardware macros within the ELF file, software functions like printf can be substituted, taking only a few cycles to capture and deliver output to host tools for decoding and analysis. Leveraging these counters and macros allows extensive profiling information and performance indicators with little to no impact on application behavior.

The Final Note

Integrating hardware modules into a RISC-V design to facilitate software debugging tools entails additional area cost and verification prerequisites that necessitate forethought, primarily because embedded software engineers are anticipated to be the primary users of the data captured by the hardware in the later stages of the device lifecycle.

Nevertheless, the advantages are considerable, given that the data collected by the hardware can furnish software engineers with the essential information required to comprehend how their applications perform under the most demanding real-world operating conditions.

The amalgamation of software and hardware tools has the potential to decrease development duration, enhance both processor and application performance, achieve complete code coverage, and diminish the crucial time required to bring a product to market.

ACL Digital provides a comprehensive suite of hardware and software tools designed to expedite the debugging process of RISC-V-based System on Chips (SoCs).

Also, ACL Digital is delighted to announce our participation as a Silver sponsor in the much-anticipated RISC-V Summit North America 2023, and we 're enthusiastic about inviting you to join us at Booth S-14! We're excited to meet and share ideas with you at the RISC-V Summit.


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