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Staff Design Engineer
- Requires Bachelor’s Degree in Electronics Engineering, Electrical Engineering or a closely related field.
- CalSoft Labs, Inc., 2890, Zanker Road, Suite 200, San Jose, CA 95134, USA
Roles & Responsibilities:
- Act as a Technical lead for DFT activities like Logic insertion, ATPG and silicon Bring-up.
- Demonstrate expertise in scan insertion for block and chip level.
- Demonstrate expertise in ATPG, Coverage Analysis, Transition delay test coverage analysis.
- Complete diagnosis of test patterns on silicon.
- Demonstrate expertise in mission mode PLL bring-up as well as boundary scan verification (JTAG/IJTAG)
- Perform RTL and Gate level simulations of scan and MBIST test vectors
- Define the test mode timing constraints and improve timing fixes/corrective actions for timing violations.
- Perform equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax/Cadence/Tk)
- Demonstrate Strong debug skills and demonstrate experience in Tcl and Perl scripting
- Collaborating with designers on STA, physical, power, and logical issues to integrate the DFT features into the design
- Generate structural test patterns and analyzing and improving coverage.
- Multi-tasking & work on several high priority designs in parallel.