Functional Safety for the RISC-V Processor & Its Sub-system

The development of the RISC-V standard has experienced significant growth in recent years. It allows anyone to design and manufacture processors based on the RISC-V specifications without license fees or royalties. The RISC-V Instruction Set Architecture (ISA) is designed to be simple, efficient, and flexible, owing to which businesses globally are leveraging RISC-V for a wide gamut of applications, including Artificial Intelligence (AI) image sensors, AI computing, Machine Control Systems in 5G networks, sophisticated Machine Learning Applications, graphics, storage, and security management systems.

With the increasing demand for intricate and safety-critical systems, adhering to the highest functional safety standards cannot be overstated. As an early adopter of RISC-V, ACL Digital possesses robust capabilities in designing and developing highly scalable multi-cluster, multi-core, and multi-threaded RISC-V cores. Functional Safety stands out as a cornerstone of ACL Digital’s RISC-V offerings. Watch our recorded webinar, “Functional Safety for the RISC-V Processor & Its Sub-system,” to delve into the latest advancements and best practices in Functional Safety (FuSa) for critical systems across various industries.