At ACL Digital, we give you the most suitable and customized design and layout on various analog IPs & high-speed interface IPs such as DDR PHY, USB 2.0, MIPI PHY, and even power management IPs.
Our team has in-depth expertise in Analog Design and Layout, Memory Design and Layout, Compiler Design and Layout, Standard Cell libraries design, and I/O development. We have worked on data converters, Bandgap references, UVLOs, and almost all predominant armories.
Services
Memory Design and Layout
- Single/Multi-Port
- SRAM
- Register Files
- Mask Progg ROM
- TCAM
- Pseudo DP RF
- Asynchronous RF
Analog Design and Layout
- PLL Design
- LVDS Design
- LDO Design
- Bandgap Design
- DC to DC Converter
Standard Cell
- High Speed Lib
- High Density Lib
- Low Power Lib
- Multichannel Lib
- Multi-VT Lib
I/O Development
- GPIO Design
- Low speed I/O Buffer
- Open drain, CMOS Buffer Design
- Input Buffer with Hysteresis Design
- PCI 33 MHz and PCI 66 MHz Design