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Lead Design Engineer

Location
San Jose
Experience
3-5
Years
Job Code
22CSL06

Preferred Education:

  • Requires Bachelor’s degree in Electronics and Communication Engineering, Computer Engineering, Information  technology, Information and Communication Engineering or closely related field.

Location:

  • CalSoft Labs, Inc., 2890, Zanker Road, Suite 200, San Jose, CA 95134, USA

Contact Person:

  • jobsus@altencalsoftlabs.com

Experience:

  • BS 3 to 5 years

Roles & Responsibilities:

  • Perform Digital design addition to ASIC for detecting manufacturing defects and improving the overall yield thus reducing defective parts per million.
  • Develop comprehensive test plan for structural validation of complex SoCs.
  • Verify design integrity at RTL level using embedded programmable built-in self-test.
  • Implement Logic built-in self-test to enable on-field testing of highly secure, especially automotive SoCs.
  • Responsible for Testability feature addition using SCAN insertion methodology to target faults on internal nodes of ASIC.
  • Demonstrate Strong experience in SCAN implementation at IP level and on SoCs.
  • Integrate Compression logic for scan implemented design to reduce test data volume and test time.
  • Perform structural integration of built in self-test for embedded memory testing.
  • Develop test plan development and validating algorithms for Programmable BIST, Memory BIST with EDA tools for large complex SoCs.
  • Develop program Test Access Port (IEEE 1149.1) for test mode entry to validate silicon.
  • Generate automated test patterns for IP and SoC using EDA tools for various fault models
  • Analyze coverage and debug to meet test mode specific coverage targets
  • Test Pattern validation using gate level simulation (GLS)
  • Work with PD engineers for timing constraints generation.
  • Work with STA Engineers on test timing and validate patterns with timing closure
  • Responsible for successful pattern handoff to tester.
  • Perform Post silicon production bring up.
  • Provide ATE debug support.
  • Contribution to DFT flow enhancement using scripting languages such as Verilog, Perl and TCL in UNIX environment.
  • Handle resource planning, Project execution plan and review.
  • Perform statement of work analysis and risk assessment.
  • Meet timelines on planned project milestones and reviews.
  • Analyze performance of employees; and
  • Perform employee goal setting and Employee Development Plan review.
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