Our team of highly experienced implementation and Design-for-Test (DFT) engineers use the best in a class design flow that uses either Synopsys IC Compiler II or Cadence Innovus Implementation System for physical design, the Mentor Tessent Suite for DFT, and Mentor Calibre for physical verification and sign-off. Our services range from RTL-to-GDSII block-level implementation for mixed-signal analog-on-top design to hierarchical digital design in leading-edge nodes.

We have experience with a variety of process nodes from 350nm to 5nm FinFet and FDSOI technology. Our foundry experience includes working with TSMC, Global Foundries, UMC, and SMIC.

DFT design

 

Our team has experience in low-power implementation using UPF (Unified Power Format), integration of RF IPs such as Wi-Fi and BLE (Bluetooth Low-Energy) as well as the integration and testing of high-speed SerDes (Serializer/Deserializer) interfaces and data converters.

Our implementation services cover

  • System installation
  • Systems maintenance
  • Operators and maintenance training
  • Mechanical and electrical installation
  • Customized quality and safety checklists
  • Cost containment
  • System acceptance testing