“C” to FPGA and Software
Overview
The customer required Design and Development of large OFDM MIMO System with Complete ownership of Software and hardware life cycle management, along with system Architecture and component selection.
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Challenges
Eight FPGAs were required to implement the logic and it involved complex algorithm understanding and implementation
Power requirement, interface and synchronization between FPGA’s Configuration, 10G MAC interface with higher layer without stack in FPGA
Complexity in realization of optimistic RTL from Matlab/C Model and Turbo Decoder from third party vendors supporting up to 35 Mbps speed. VHDL/Verilog is used for RTL Design.
Solution
- VHDL based Testbench for unit level and top level verification
- Altera Quartus 13.0 for synthesis and Questasim for simulation
- Functional Coverage driven test planning methodology
- Design consisted of TMAC, Transmitter and Receiver
Outcomes
- Matlab algorithm implementation
- Floating to Fixed point conversion and BER Measurement
- Fixed point and C-Model to RTL Conversion
- Implemented in Altera Stratix-V FPGA’s and Cyclone V FPGA (28nm technology)
