Overview
The customer is a Fabless Semiconductor Company and wanted a partner for a low power IoT derivative chip.
Challenges
- IP Max frequency of 6GHz and controller frequency of 1.5GHz
- Mainstream High Performance process node, FPBGA
- WLAN -960MHz max, ARM CR4 - 360MHz, BT - 96 MHz. DSP – 96MHz
- Peripherals: PCIE, SMIF, SDIO, UART, I2C, SPI, PCM, I2S, JTAG, SWD and CoEx
- PPA Optimization
- RF Co-existence with High Speed Digital
- Complex Low Power State Machine Verification
Outcomes
Implementation of (RTL2GDSII)
Analyzed the Channel Length, VT analysis and its usage based on PPA targets
Worked with RTL and DFT teams, to define modes and corners
Kept switchable devices away from sensitive RF. Interference aware clocking scheme
DVFS aware STA corner definitions and analysis
Switchable domain. UPF development from scratch